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19-3754; Rev 0; 8/05
Constant-Frequency, Half-Bridge CCFL Inverter Controller
General Description
The MAX8729 cold-cathode-fluorescent lamp (CCFL) inverter controller is designed to drive multiple CCFLs using the half-bridge inverter consisting of two external n-channel power MOSFETs. The half-bridge topology minimizes the component count, while providing near sinusoidal drive waveforms. The MAX8729 operates in resonant mode during striking and switches over to constant-frequency operation after all the lamps are lit. This unique feature ensures reliable striking under all conditions and reduces the transformer stress. The MAX8729 provides accurate lamp-current regulation (2.5%). The lamp current is adjustable with an external resistor. The MAX8729 changes the brightness by turning the CCFL on and off using a digital pulse-width modulation (DPWM) method, while maintaining the lamp current constant. The brightness can be adjusted with an analog voltage on the CNTL pin, or with an external PWM signal. The MAX8729 is capable of synchronizing and adjusting the phase of the gate drivers and DPWM oscillator. These features allow multiple MAX8729 ICs to be connected in a daisy-chain configuration. The switching frequency and DPWM frequency of the master IC can be easily adjusted using external resistors, or synchronized with system signals. If the controller loses the external sync signals, it switches over to the internal oscillators and keeps operating. Phase-shift select pins PS1 and PS2 can be used to program four different phase shifts, allowing up to five MAX8729s to be used together. The MAX8729 protects the inverter from lamp-out, secondary overvoltage, and secondary short-circuit faults. The MAX8729 can drive large-power MOSFETs typically used in applications where one power stage drives four or more CCFL tubes in parallel. An internal 5.35V linear regulator powers the MOSFET drivers and most of the internal circuitry. The MAX8729 is available in a low-cost, 28-pin QSOP package and operates over the -40C to +85C extended temperature range.
Features
Low-Cost, Half-Bridge Inverter Topology Resonant Mode Striking Ensures Startup Constant-Frequency Operation After Lamp Ignition Drives Large External MOSFETs Supports Multilamp Applications Sync and Phase-Shift Controls Allow DaisyChained Operation Adjustable Switching Frequency and DPWM Frequency 2.5% Lamp-Current Regulation 10:1 Dimming Range Accurate Analog-Dimming Control Lamp-Out Detection with Adjustable Timeout Secondary Current and Voltage Limiting Primary Current Limit with RDS(ON) Sensing Adjustable DPWM Rise and Fall Time Low-Cost, 28-Pin QSOP Package
MAX8729
Simplified Operating Circuit
INPUT VCC 3 IN 5 GND VCC ON/OFF DIMMING 4 VCC 8 SHDN 7 CNTL 2 SEL 12 PSCK 22 PS1 16 PS2 15 HF LX 23 GL 27 PGND 26 VFB 19 ISEC 20 IFB 18 COMP 17 MAX8729 9 LF TFLT 6 VDD 28
BST 25 GH 24
CCFL
Applications
LCD Monitors LCD TVs Notebook Computers Automotive Infotainment
Ordering Information
PART MAX8729EEI TEMP RANGE -40C to +85C PIN-PACKAGE 28 QSOP
11 DPWM 13 HFCK 10 LFCK
PCOMP 1 HSYNC 14 LSYNC 21
Pin Configuration appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products
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Constant-Frequency, Half-Bridge CCFL Inverter Controller MAX8729
ABSOLUTE MAXIMUM RATINGS
IN, LX to GND.........................................................-0.3V to +30V BST to GND ............................................................-0.3V to +36V BST to LX..................................................................-0.3V to +6V VCC, VDD to GND......................................................-0.3V to +6V GH to LX ......................................................-0.3V to VBST + 0.3V CNTL, COMP, GL, DPWM, HF, LF, HFCK, LFCK, HSYNC, LSYNC, PS1, PS2, PSCK, TFLT, PCOMP, SEL ......................................................-0.3V to VCC + 0.3V IFB, ISEC, VFB to GND................................................-6V to +6V SHDN to GND...........................................................-0.3V to +6V PGND to GND .......................................................-0.3V to +0.3V Continuous Power Dissipation (TA = +70C) 28-Pin QSOP (derate 10.8mW/C above +70C)......860.2mW Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VIN = 12V, VDD = 5.3V, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER IN Input Voltage Range IN Quiescent Current IN Quiescent Current, Shutdown VCC Output Voltage, Normal Operation VCC Output Voltage, Shutdown VCC Undervoltage Lockout Threshold VCC Undervoltage-Lockout Hysteresis GH, GL On-Resistance, Low State GH, GL On-Resistance, High State BST Leakage Current Resonant Frequency Range Minimum Off-Time Maximum Off-Time (LX-GND) Low-Side MOSFET Maximum Current-Limit Threshold (LX-GND) High-Side MOSFET Maximum Current-Limit Threshold (IN - LX) Low-Side MOSFET Zero-CurrentCrossing Threshold (GND - LX) High-Side MOSFET Zero-CurrentCrossing Threshold (LX - IN) Current-Limit Leading Edge Blanking IFB Regulation Point IFB Maximum AC Voltage Internally full-wave rectified ITEST = 10mA ITEST = 10mA VBST = 17V, VLX = 12V Not tested 30 330 24.0 370 370 0 -16 310 770 416 30.7 400 400 10 +6 410 790 3 VSHDN = 5.3V, VIN = 28V SHDN = GND VSHDN = 5.3V, 6V < VIN < 28V, 0 < ILOAD < 10mA SHDN = GND, no load VCC rising (leaving lockout) VCC falling (entering lockout) 4.0 200 1 4 2 6 5 80 560 42.0 470 470 18 +28 560 810 5.20 3.5 CONDITIONS MIN 6 3.2 6 5.35 4.6 TYP MAX 28 6 20 5.50 5.5 4.5 UNITS V mA A V V V mV A kHz ns s mV mV mV mV ns mV V
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Constant-Frequency, Half-Bridge CCFL Inverter Controller
ELECTRICAL CHARACTERISTICS (continued)
(VIN = 12V, VDD = 5.3V, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER IFB Input Bias Current IFB Lamp-Out Threshold IFB-to-COMP Transconductance COMP Output Impedance COMP Discharge Current During Overvoltage or Overcurrent Fault COMP Discharge Current During DPWM Off-Time ISEC Input Voltage Range ISEC Input Bias Current ISEC Overcurrent Threshold VFB Input-Voltage Range VFB Input Bias Current VFB Overvoltage Threshold Main Oscillator Frequency Main Oscillator Frequency Range HF, HFCK, LF, LFCK Input-Low Voltage HF, HFCK, LF, LFCK Input-High Voltage HF, HFCK, LF, LFCK Input Hysteresis HF, HFCK, LF, LFCK Input Bias Current HF, HFCK, LF, LFCK Input Rise and Fall Time HF Input Frequency Range HFCK Input Frequency Range HSYNC Input Frequency Range LF Input Frequency Range LFCK Input Frequency Range LSYNC Input Frequency Range DPWM Chopping Frequency DPWM Frequency Range Slave mode, VCNTL = VCC Slave mode, VCNTL = VCC Slave mode, VCNTL = VCC Slave mode, VCNTL = VCC Slave mode, VCNTL = VCC Slave mode, VCNTL = VCC Slave mode, VCNTL = VCC RHF = 100k Slave mode, VCNTL = VCC Slave mode, VCNTL = VCC RLF = 150k RLF = 150k RLF = 300k 20 120 190 80 10.24 120 199 80 207 -1 2.1 200 +1 200 100 600 460 300 38.40 280 215 300 RHF = 100k -4V < VVFB < 4V VIFB = 800mV, VISEC = 2.5V CNTL = GND, VCOMP = 1.5V -3 -0.3 1.18 -4 -25 2.15 51.7 20 2.25 53.8 1.21 0 < VIFB < 2V -2V < VIFB < 0 Reject 1s glitches 0.5V < VCOMP < 2.4V CONDITIONS MIN -3 -150 760 790 100 10 1200 100 +3 +0.3 1.26 +4 +25 2.35 55.9 100 0.8 820 TYP MAX +3 UNITS A mV S M A A V A V V A V kHz kHz V V mV A ns kHz kHz kHz Hz kHz Hz Hz Hz
MAX8729
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Constant-Frequency, Half-Bridge CCFL Inverter Controller MAX8729
ELECTRICAL CHARACTERISTICS (continued)
(VIN = 12V, VDD = 5.3V, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER PS1, PS2, LSYNC, HSYNC, SEL Input Low Voltage PS1, PS2, LSYNC, HSYNC, SEL Input High Voltage PS1, PS2, LSYNC, HSYNC, SEL Input Hysteresis PS1, PS2, LSYNC, HSYNC, SEL Input Bias Current HFCK, LFCK, PSCK, DPWM Output On-Resistance CNTL Minimum Duty-Cycle Threshold CNTL Maximum Duty-Cycle Threshold CNTL Input Current CNTL Input Threshold DPWM A/D Converter Resolution SHDN Input Low Voltage SHDN Input High Voltage SHDN Input Bias Current VISEC < 1.25 and VIFB < 790mV; VFLT = 2.0V TFLT Charging Current TFLT Trip Threshold VISEC < 1.25 and VIFB > 790mV; VFLT = 2.0V VISEC > 1.25 and VIFB < 790mV; VFLT = 2.0V 3.9 2.1 -1 0.95 1.00 -1 126 4.0 4.1 V +1 1.05 A 0 < VCNTL < 2V Slave mode Guaranteed monotonic ITEST = 1mA 0.21 1.9 -0.1 4.2 4.5 5 0.8 0.23 2.0 -1 2.1 200 +1 2.5 0.26 2.1 +0.1 4.8 CONDITIONS MIN TYP MAX 0.8 UNITS V V mV A k V V A V Bits V V A
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Constant-Frequency, Half-Bridge CCFL Inverter Controller
ELECTRICAL CHARACTERISTICS
(VIN = 12V, VDD = 5.3V, TA = -40C to +85C, unless otherwise noted.) (Note 1)
PARAMETER IN Input-Voltage Range IN Quiescent Current IN Quiescent Current, Shutdown VCC Output Voltage, Normal Operation VCC Output Voltage, Shutdown VCC Undervoltage Lockout Threshold GH, GL On-Resistance, Low State GH, GL On-Resistance, High State Minimum Off-Time Maximum Off-Time Low-Side MOSFET Maximum Current-Limit Threshold (LX - GND) High-Side MOSFET Maximum Current-Limit Threshold (IN - LX) Low-Side MOSFET Zero-Current Crossing Threshold (GND - LX) High-Side MOSFET Zero-Current Crossing Threshold (LX - IN) Current-Limit Leading-Edge Blanking IFB Regulation Point IFB Maximum AC Voltage IFB Input Bias Current IFB Lamp-Out Threshold ISEC Input Voltage Range ISEC Overcurrent Threshold VFB Input Voltage Range VFB Overvoltage Threshold Main Oscillator Frequency Main Oscillator Frequency Range RHF = 100k 0 < VIFB < 2V -2V < VIFB < 0 Reject 1s glitches -3 -150 760 -3 1.18 -4 2.15 50.0 20 820 +3 1.26 +4 2.35 57.6 100 Internally full-wave rectified VSHDN = 5.3V, VIN = 28V SHDN = GND VSHDN = 5.3V, 6V < VIN < 28V, 0 < ILOAD < 10mA SHDN = GND, no load VCC rising (leaving lockout) VCC falling (entering lockout) ITEST = 10mA ITEST = 10mA 330 24.0 350 4.0 3 7 560 42.0 500 5.20 3.5 CONDITIONS MIN 6 TYP MAX 28 6 20 5.50 5.5 4.5 UNITS V mA A V V V ns s mV
MAX8729
350 0 -16 310 770 3
500 18 +28 560 810 +3
mV mV mV ns mV V A mV V V V V kHz kHz
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Constant-Frequency, Half-Bridge CCFL Inverter Controller MAX8729
ELECTRICAL CHARACTERISTICS (continued)
(VIN = 12V, VDD = 5.3V, TA = -40C to +85C, unless otherwise noted.) (Note 1)
PARAMETER HF, HFCK, LF, LFCK Input Low Voltage HF, HFCK, LF, LFCK Input High Voltage HF, HFCK, LF, LFCK Input Rise and Fall Time HF Input Frequency Range HFCK Input Frequency Range HSYNC Input Frequency Range LF Input Frequency Range LFCK Input Frequency Range LSYNC Input Frequency Range DPWM Chopping Frequency DPWM Input Frequency Range PS1, PS2, LSYNC, HSYNC, SEL Input Low Voltage PS1, PS2, LSYNC, HSYNC, SEL Input High Voltage HFCK, LFCK, PSCK, DPWM Output On-Resistance CNTL Minimum Duty-Cycle Threshold CNTL Maximum Duty-Cycle Threshold CNTL Input Threshold SHDN Input Low Voltage SHDN Input High Voltage TFLT Charging Current TFLT Trip Threshold VISEC < 1.25 and VIFB < 600mV, VFLT = 2.0V 2.1 0.93 3.9 1.07 4.1 Slave mode ITEST = 1mA 0.21 1.9 4.2 2.1 2.5 0.26 2.1 4.8 0.8 CONDITIONS Slave mode, VCNTL = VCC Slave mode, VCNTL = VCC Slave mode, VCNTL = VCC Slave mode, VCNTL = VCC Slave mode, VCNTL = VCC RHF = 100k Slave mode, VCNTL = VCC Slave mode, VCNTL = VCC RLF = 150k RLF = 150k 20 120 190 80 10.24 120 197 80 2.1 200 100 600 460 300 38.40 280 217 300 0.8 MIN TYP MAX 0.8 UNITS V V ns kHz kHz kHz Hz kHz Hz Hz Hz V V k V V V V V A V
Note 1: Specifications to -40C are guaranteed by design, based on final characterization results.
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Constant-Frequency, Half-Bridge CCFL Inverter Controller MAX8729
Typical Operating Characteristics
(Circuit of Figure 1. VIN = 12V, VCC = VDD, TA = +25C, unless otherwise noted.)
NORMAL OPERATION
MAX8729 toc01
MINIMUM BRIGHTNESS STARTUP WAVEFORM
MAX8729 toc02
MINIMUM BRIGHTNESS DPWM OPERATION
MAX8729 toc03
A B B
B A A C C 4ms/div A: COMP, 1V/div B: IFB, 2V/div C: VFB, 2V/div 1ms/div C
A: LX, 10V/div B: IFB, 2V/div C: VFB, 2V/div
A: IFB, 2V/div B: VFB, 1V/div C: COMP, 1V/div
2ms/div
50% BRIGHTNESS DPWM OPERATION
MAX8729 toc04
DPWM SOFT-START
MAX8729 toc05
DPWM SOFT-STOP
MAX8729 toc06
A A A
C
B
B
B
C C
A: IFB, 2V/div B: VFB, 1V/div C: COMP, 1V/div
2ms/div A: IFB, 2V/div B: VFB, 1V/div C: COMP, 1V/div
100ms/div
A: IFB, 2V/div B: VFB, 1V/div C: COMP, 1V/div
100ms/div
LAMP-OUT VOLTAGE LIMITING AND TIMEOUT
MAX8729 toc07
SECONDARY SHORT-CIRCUIT PROTECTION AND TIMEOUT
MAX8729 toc08
SWITCHING FREQUENCY vs. RHF
70 A SWITCHING FREQUENCY (kHz) 65 60 55 50 45 40
MAX8729 tc09
C
75
1.17s
A 25.4ms
B 400ms/div 10ms/div
C
A: COMP, 2V/div B: VFB, 2V/div C: TFLT, 5V/div
A: ISEC, 1V/div B: COMP, 2V/div C: TFLT, 5V/div
75
85
95
105 115 RHF (k)
125
135
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Constant-Frequency, Half-Bridge CCFL Inverter Controller MAX8729
Typical Operating Characteristics (continued)
(Circuit of Figure 1. VIN = 12V, VCC = VDD, TA = +25C, unless otherwise noted.)
DPWM FREQUENCY vs. RLF
MAX8729 toc10
DPWM FREQUENCY vs. INPUT VOLTAGE
MAX8729 toc11
LAMP CURRENT vs. RSENSE
MAX8729 toc12
500
208.0
9
DPWM FREQUENCY (Hz)
DPWM FREQUENCY (Hz)
400
207.5 LAMP CURRENT (mA) 8 12 16 INPUT VOLTAGE (V) 20
8
7
300
207.0
6
200
206.5
5 100 75 125 175 225 RLF (k) 275 325 206.0
4 110 130 150 170 190 RSENSE () 210 230
VCC LINE REGULATION
MAX8729 toc13
VCC LOAD REGULATION
MAX8729 toc14
VCC vs. TEMPERATURE
VIN = 12V NOT SWITCHING 5.38
MAX8729 toc15
5.370
5.39
5.40
5.362
5.37
VCC (V)
VCC (V)
VCC (V)
5.354
5.35
5.36
5.346
5.33
5.34
5.338
5.31
5.32
5.330 8 11 14 17 INPUT VOLTAGE (V) 20
5.29 0 2 4 6 8 10 LOAD CURRENT (mA)
5.30 -40 -15 10 35 TEMPERATURE (C) 60 85
DPWM PHASE SHIFT (90)
MAX8729 toc16
SWITCHING PHASE SHIFT (90)
MAX8729 toc17
A
B
B
A
2ms/div A: SLAVE DPWM 5V/div B: MASTER DPWM 5V/div
4ms/div A: SLAVE DPWM B: MASTER DPWM
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Constant-Frequency, Half-Bridge CCFL Inverter Controller MAX8729
Typical Operating Characteristics (continued)
(Circuit of Figure 1. VIN = 12V, VCC = VDD, TA = +25C, unless otherwise noted.)
HF SYNCHRONIZATION
MAX8729 toc18 MAX8729 toc19
LF SYNCHRONIZATION
A
A B B C 4ms/div A: HSYNC, 5/div B: HFCK, 5/div C: IFB, 2V/div
4ms/div A: LSYNC 5/div B: COMP 2V/div
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Constant-Frequency, Half-Bridge CCFL Inverter Controller MAX8729
Pin Description
PIN 1 NAME PCOMP FUNCTION Compensation Node of the Phase-Lock Loop. Connect a 0.1F capacitor between PCOMP and GND to compensate the phase-lock loop. Brightness-Control Select Input. Brightness can be adjusted with an analog voltage or with an external sync signal. Connecting SEL to GND enables analog control at the CNTL pin. Connecting SEL to VCC enables brightness control using an external sync signal at the LSYNC pin. Supply Input. Input to the internal 5.35V linear regulator that powers the device. Bypass IN to GND with a 0.1F ceramic capacitor. 5.35V/10mA Linear-Regulator Output. VCC powers most of the control circuitry in the MAX8729. Bypass VCC to GND with a 1F ceramic capacitor. System Ground Fault-Timer Set Pin. Connect a 0.22F capacitor from TFLT to GND to set the open-lamp fault delay period to approximately 1.2s and the secondary short-circuit fault-delay period to approximately 10ms. See the Setting the Fault-Delay Time section for details. Brightness Control Input. The usable brightness control range is from 0 to 2V. VCNTL = 0 represents the minimum brightness (10% DPWM duty cycle); 2V VCNTL < 4.2V represents the full brightness (100% DPWM duty cycle). The MAX8729 enters into slave mode when CNTL is connected to VCC. See the Digital PWM Dimming Control section for details. Shutdown Control Input. The MAX8729 shuts down when SHDN is pulled to GND. DPWM Frequency Adjustment Pin. Connect a resistor from LF to GND to set the DPWM oscillator frequency. LF is a logic input when CNTL is connected to VCC. DPWM Oscillator Clock Output. LFCK is a logic input when CNTL is connected to VCC. DPWM Signal Output. The DPWM output is used to control the DPWM frequency of the slave IC in master-slave operation. See the Slave Operation section for details. Phase-Shift Clock Output. PSCK is a logic input when CNTL is connected to VCC. Main Switching Oscillator Clock Output. HFCK is a logic input when CNTL is connected to VCC. Main Switching-Frequency Sync Input. Switching frequency can be synchronized with an external signal on HSYNC. HSYNC has a Schmitt trigger input. Switching-Frequency Adjustment Pin. Connect a resistor from HF to GND to set the main oscillator frequency. HF is a logic input when CNTL is connected to VCC. Phase-Shift Select Input. The PS1 and PS2 logic inputs select between four programmable phase shifts (60, 90, 120, and 180) in master-slave operation. PS1 and PS2 should be in identical states in each slave. See the Phase Shift section for details. Transconductance Error-Amplifier Output. A 0.01F capacitor connected between COMP and GND sets the rise and fall time of the lamp-current envelope during DPWM operation. See the COMP Capacitor Selection section for details.
2
SEL
3 4 5 6
IN VCC GND TFLT
7
CNTL
8 9 10 11 12 13 14 15
SHDN LF LFCK DPWM PSCK HFCK HSYNC HF
16
PS2
17
COMP
10
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Constant-Frequency, Half-Bridge CCFL Inverter Controller
Pin Description (continued)
PIN NAME FUNCTION Lamp-Current Feedback Input. The IFB sense signal is internally full-wave rectified. The average value of the rectified signal is regulated to 790mV (typ) by controlling the on-time of the high-side MOSFET. An open-lamp fault is generated if the IFB is continuously below 790mV (typ) for a period set by TFLT. See the Lamp-Out Protection and Setting the Fault-Delay Time sections for details. Transformer Secondary-Voltage Feedback Input. When the peak voltage on VFB exceeds the 2.3V (typ) overvoltage threshold, the controller turns on an internal 1.2mA current sink, discharging the COMP capacitor. A capacitive voltage-divider between the high-voltage terminal of the CCFL tube and GND determines the maximum lamp output voltage during startup and lamp-out fault. See the Setting the Secondary Voltage Limit section for details. Transformer Secondary-Current Feedback Input. When the peak voltage on ISEC exceeds the internal overcurrent threshold, the controller turns on an internal 1.2mA current sink, discharging the COMP capacitor. A current-sense resistor connected between the low-voltage end of the transformer secondary and the ground determines the maximum secondary current during short-circuit fault. See the Setting the Secondary Current Limit section for details. DPWM Sync Input. DPWM frequency can be synchronized with an external signal on LSYNC. When SEL is connected to VCC, the duty cycle of the LSYNC signal determines the brightness. LSYNC has a Schmitt trigger input. Phase-Shift-Select Input. The PS1 and PS2 logic inputs select between four programmable phase shifts (60, 90, 120, and 180) in master-slave operation. PS1 and PS2 should be in identical states in each slave. See the Phase Shift section for details. Switching Node. LX is the return of the high-side gate driver. LX is also the input to the primary current-limit and zero-crossing comparators. The controller senses the voltage across the high-side MOSFET (IN - LX) and low-side MOSFET (LX - GND) to detect primary overcurrent condition and zero crossing. High-Side MOSFET Gate-Driver Output High-Side Gate-Driver Supply Input. The MAX8729 includes an integrated boost diode. Connect a 0.1F capacitor between LX and BST to complete the bootstrap circuit. Power Ground. PGND is the return for the low-side gate driver. Low-Side MOSFET Gate-Driver Output Low-Side MOSFET Gate-Driver Supply Input
MAX8729
18
IFB
19
VFB
20
ISEC
21
LSYNC
22
PS1
23
LX
24 25 26 27 28
GH BST PGND GL VDD
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Constant-Frequency, Half-Bridge CCFL Inverter Controller MAX8729
INPUT 7V TO 24V F1 1A C9 10F C1 2.2F
VCC 3 C10 0.1F VCC ON/OFF 5 4 C12 1F 8 DIMMING 7 2 12 22 16 15 R3 100k 1% 9 R4 150k 1% 11 DPWM 13 R5 1M R6 1M 10 HFCK LFCK 1 14 21 C7 0.1F LF TFLT 6 C6 0.22F SHDN LX CNTL SEL GL PSCK PS1 PS2 IFB HF COMP PGND VFB ISEC 27 26 19 20 18 17 C5 0.01F R2 40.2 C4 10nF T1 N2 C3 10pF 3kV 23 IN GND VCC VDD 28 C11 1F 25 24 C8 0.1F N1
MAX8729
BST GH
C2 2.2F
CCFL
R1 160 1%
PCOMP HSYNC LSYNC
Figure 1. Typical Stand-Alone Operating Circuit
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Constant-Frequency, Half-Bridge CCFL Inverter Controller MAX8729
IN GND VCC OVERVOLTAGE COMPARATOR 2.3V VFB COMP OVERCURRENT 100A
LINEAR REGULATOR
BIAS SUPPLY
EN FLT UVLO
MAX8729
SHDN PS1 PHASE SELECT PS2 PSCK
4.2V UVLO COMPARATOR RAMP 1.2mA HIGHFREQ OSC
HSYNC HFCK HF LSYNC
PWM COMPARATOR
PLL AND DPWM OSC
LFCK LF PCOMP
IFB
F.W. RECT 790mV ERROR AMPLIFIER PWM CONTROL LOGIC
BST GH GATE-DRIVER CONTROL STATE MACHINE LX VDD GL OPEN-LAMP COMPARATOR FAULT-DELAY BLOCK PRIMARY OVERCURRENT AND ZERO CROSSING SELECT LX MUX IN S 1.25V SECONDARY OVERCURRENT COMPARATOR SHDN UVLO Q RESET R FAULT LATCH FLT PGND
DPWM SEL CNTL DIMMING CONTROL LOGIC
790mV
OVERCURRENT
ISEC
TFLT
Figure 2. Functional Diagram
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Constant-Frequency, Half-Bridge CCFL Inverter Controller MAX8729
Detailed Description
Figure 1 shows the Stand-Alone Typical Operating Circuit. Figure 2 shows the Functional Diagram of the MAX8729. The circuit architecture consists of a halfbridge inverter, which converts unregulated DC into a nearly sinusoidal, high-frequency, AC output for powering CCFLs. The MAX8729 is biased from an internal 5.35V linear regulator with UVLO comparator that ensures stable operation and clean startup characteristics. There are several layers of fault-protection circuitry, consisting of comparators for detecting primary-side current limit, secondary-side overvoltage, secondary short circuit, and open-lamp faults. A logic block arbitrates the comparator outputs by making sure that a given fault persists for a minimum duration before registering the fault condition. A separate block provides dimming control based upon analog or DPWM inputs. Finally, a dedicated logic circuit provides synchronization and phase control functions for daisy chaining up to five MAX8729s without phase overlap. The inverter operates in resonant mode during striking and switches over to constant-frequency operation after all the lamps are lit. This unique feature ensures reliable striking under all conditions and reduces the transformer stress. The constant-frequency architecture can be synchronized and phase shifted for daisychained applications. Multiple lamps can also be driven in parallel within a single stage. The MAX8729's gate drivers are strong enough to drive the large-power MOSFETs needed when one power stage drives four or more CCFL lamps in parallel. The MAX8729 provides accurate lamp-current regulation (2.5%). A primary-side current sense provides cycleby-cycle current limit and zero-crossing detection, while the secondary current is sensed with a separate loop that provides fine adjustment of the lamp current with an external resistor. The MAX8729 controls lamp brightness by turning the CCFL on and off using a DPWM method, while maintaining approximately constant lamp current. The brightness set point can be adjusted with an analog voltage on the CNTL pin, or with an external PWM signal. The MAX8729 has a single compensation input (COMP), which also establishes the soft-start and softstop timing characteristics. Control logic changes the available drive current at COMP based on the operating mode to adjust the inverter's dynamic behavior.
Constant-Frequency Operation
The MAX8729 operates in constant-frequency mode in normal operation. There are two ways to set the switching frequency: 1) The switching frequency can be set with an external resistor connected between HF and GND. The switching frequency is given by the following equation: fSW = 54kHz x 100k RHF
The adjustable range of the switching frequency is between 20kHz and 100kHz (RHF is between 270k and 54k). 2) The switching frequency can be synchronized by an external high-frequency signal. Connect HF to GND through a 100k resistor, and connect HSYNC to the external high-frequency signal. The resulting synchronized switching frequency (fSW) is 1/6th the frequency of the external signal (fEXT): f fSW = EXT 6 The frequency range of the external signal should be between 190kHz and 460kHz, with RHF + 100k resulting in a switching frequency range between 32kHz and 77kHz. Figure 3 illustrates the constant-frequency operation, with timing diagrams that show the primary current, clock signal, and gate-drive signals. At the beginning of the positive half cycle, the high-side switch is on and the primary current ramps up. The controller turns off the high-side switch at t1. The primary current continues to flow in the same direction, which forward biases the body diode of the low-side switch after the highside switch is off. When the controller turns on the lowside switch, the voltage drop across the switch is nearly zero. This zero-voltage switching (ZVS) operation results in lower switching losses. With DL on, the primary current ramps down. If the primary current reaches zero (t2) before the falling edge of the oscillator clock arrives (t3), as shown in Figure 3(A), the controller turns off the low-side switch at t 2 . Both the high-side switch and low-side switch stay off until t3. The controller turns on the low-side switch at the falling edge of the clock (t3). The primary current ramps up in the other direction, starting the negative half cycle. If the clock falling edge comes before the zero crossing as shown in Figure 3(B), the low-side switch stays on, which allows the primary current to reach zero and then
14
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Constant-Frequency, Half-Bridge CCFL Inverter Controller MAX8729
PRIMARY CURRENT
CLOCK SIGNAL
DH
DL
t1 t2 t3 t4 t5 t6 (A) PRIMARY CURRENT CROSSES ZERO BEFORE CLOCK SIGNAL
PRIMARY CURRENT
CLOCK SIGNAL
DH
DL t1 t3 t4 t6 (B) PRIMARY CURRENT CROSSES ZERO AFTER CLOCK SIGNAL
Figure 3. Constant-Frequency-Operation Timing Diagram ______________________________________________________________________________________ 15
Constant-Frequency, Half-Bridge CCFL Inverter Controller MAX8729
continues below ground to start the negative cycle. During the negative half cycle, the controller turns off the low-side switch at t4. After which, the controller turns on the high-side switch under ZVS conditions and a new cycle begins. In both cases, A and B, ZVS operation reduces the turn-on switching losses of both power switches, resulting in better efficiency.
Lamp-Current Regulation
The MAX8729 uses a lamp-current control loop to regulate the current delivered to the CCFL. The heart of the control loop is a transconductance error amplifier in Figure 2. The AC lamp current is sensed with a sense resistor connected in series with the low-voltage terminal of the lamp. The voltage across this resistor is fed to the IFB input and is internally full-wave rectified. The transconductance error amplifier compares the rectified IFB voltage with a 790mV (typ) internal reference to generate an error current. The error current charges and discharges a capacitor connected between the error amplifier's output (COMP) and ground to create an error voltage (VCOMP). VCOMP is then compared with an internal ramp signal to control the high-side MOSFET switch on-time (tON).
Resonant Startup
The MAX8729 operates in resonant mode during startup. In resonant operation, the inverter keeps increasing the secondary voltage until either the lamp is struck or the controller activates overvoltage protection. In resonant mode, the switching frequency is synchronized with the natural resonant frequency of the resonant tank circuit composed of: transformer leakage inductance, primary capacitive divider, and secondary resonant capacitor. The synchronization and phase-shift functions are disabled during startup. Figure 4 demonstrates the resonant operation, with a timing diagram of the primary current and gate signals. In the resonant mode, the high side turns on at the beginning of the positive half cycle. The primary current ramps up. The controller turns off the high-side switch at t1 to regulate the lamp current. The primary current continues to flow in the same direction, which forward biases the body diode of the low-side switch after the high-side switch is off. When the controller turns on the low-side switch, the voltage drop across the switch is nearly zero. This ZVS operation results in lower switching losses. With DL on, the primary current ramps down through zero until t2, when the controller turns off the low-side switch. After which, the controller turns on the high-side switch with ZVS condition and a new cycle begins. The ZVS operation of this architecture reduces the turn-on switching losses of both power switches, resulting in better efficiency.
Transformer Secondary Voltage Limiting
The MAX8729 reduces the voltage stress on the transformer's secondary winding by limiting the secondary voltage during startup and open-lamp fault. The AC voltage across the transformer secondary winding is sensed through a capacitive voltage-divider. The voltage across the low-side capacitor of the divider is fed to the VFB input and is internally half-wave rectified. An overvoltage comparator compares the VFB voltage with a 2.3V (typ) internal threshold. Once the sense voltage exceeds the overvoltage threshold, the MAX8729 turns on a 1.2mA current source that discharges the COMP capacitor. As the COMP voltage decreases, the highside MOSFET's on-time shortens, which reduces the transformer secondary peak voltage. The MAX8729 stops discharging the COMP capacitor after the secondary peak voltage is below the threshold set by the capacitive voltage-divider. This mechanism effectively limits the secondary voltage.
Lamp Startup
A CCFL is a gas-discharge lamp that is normally driven in the avalanche mode. To start ionization in a nonionized lamp, the applied voltage (striking voltage) must be increased to the level required to start ionization in the lamp. For example, the normal running voltage of a typical CCFL is around 650VRMS, but the striking voltage can be as high as 1800VRMS. The MAX8729's unique resonant startup method ensures reliable striking. Before the lamp is ionized, the lamp impedance is infinite. The transformer secondary leakage inductance and the high-voltage parallel capacitor determine the unloaded resonant frequency. Since the unloaded resonant circuit has a high Q, the inverter keeps increasing the secondary voltage until either the lamp is struck or the controller activates the secondary overvoltage protection.
PRIMARY CURRENT
DH
DL t1 t2
Figure 4. Resonant-Operation Timing Diagram 16
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Constant-Frequency, Half-Bridge CCFL Inverter Controller
Upon power-up, VCOMP slowly rises, increasing the duty cycle of the high-side MOSFET switches and providing a measure of soft-start. In addition, the MAX8729 charges VFB to the overvoltage threshold (2.3V, typ) immediately after the device is enabled. The DC voltage on VFB is gradually discharged through an internal resistor during startup. This feature is equivalent to slowly raising the overvoltage threshold during startup, so it further improves the soft-start behavior. The MAX8729 automatically switches over to the constant-frequency operation after the lamp current reaches regulation. either from the internal oscillator or from an external signal source. In DPWM operation, COMP controls the dynamics of the lamp-current envelope. At the beginning of the DPWM ON cycle, the average value of the lamp-current feedback signal is below the regulation point, so the transconductance error amplifier sources current into the COMP capacitor. The switch on-time (tON) gradually increases as VCOMP rises, which provides soft-start. At the end of the DPWM ON cycle, the MAX8729 turns on a 100A internal current source. The current source linearly discharges the COMP capacitor, gradually decreasing tON, and providing soft-stop. Using the Internal Oscillator When the SEL pin is connected to ground, the MAX8729 uses the internal oscillator to generate the DPWM signal. The frequency of the internal DPWM oscillator is adjustable through a resistor connected between LF and GND. The DPWM frequency is given by the following equation: fDPWM = 207Hz x 150k RLF
MAX8729
Feed-Forward Control and Dropout Operation
The MAX8729 is designed to maintain tight control of the lamp current when a line transient occurs. The feed-forward control instantaneously adjusts the ontime for changes in input voltage (VIN). This feature provides immunity to input-voltage variations and simplifies loop compensation over wide-input voltage ranges. The feed-forward control also improves the line regulation for short DPWM on-times and makes startup transients less dependent on the input voltage. Feed-forward control is implemented by increasing the internal voltage ramp rate for higher VIN. This has the effect of varying tON as a function of the input voltage while maintaining about the same signal levels at VCOMP. Since the required voltage change across the compensation capacitor is minimal, the controller's response to input voltage changes is essentially instantaneous.
DPWM Dimming Control
The MAX8729 controls the brightness of the CCFL by "chopping" the lamp current on and off using a low-frequency (between 100Hz and 350Hz) DPWM signal
100 90 80 BRIGHTNESS (%) 70 60 50 40 30 20 10 0 0 400 800 1200 1600 2000 CNTL VOLTAGE (mV)
The adjustable range of the DPWM frequency is between 100Hz and 300Hz (RLF is between 217k and 103k). The CCFL brightness is proportional to the DPWM duty cycle, which can be adjusted from 10% to 100% through the CNTL pin. CNTL is an analog input with a usable input voltage range between 0 and 2V, which is digitized to select one of 128 brightness levels. As shown in Figure 5, the MAX8729 ignores the first 13 steps, so the first 13 steps all represent the same brightness. When VCNTL is between 0 and 203mV, the DPWM duty cycle is always 10%. When VCNTL is above 203mV, a 15.625mV change on CNTL results in a 0.78% change in the DPWM duty cycle. When VCNTL is equal to or above 2V, the DPWM duty cycle is always 100%. Using the External PWM Signal To use the external DPWM signal to control the brightness, connect SEL to VCC and connect LSYNC to the external signal source. The frequency range of the external signal is between 100Hz and 300Hz with RLF = 150k. In this mode, the brightness control input CNTL is disabled, and the brightness is proportional to the duty cycle of the external signal. When the duty cycle of the external signal is 100%, the CCFL reaches full brightness. If the duty cycle of the external signal is less than 10%, the CCFL brightness is adjusted accordingly.
Figure 5. Theoretical Brightness vs. Control Voltage ______________________________________________________________________________________ 17
Constant-Frequency, Half-Bridge CCFL Inverter Controller MAX8729
Lamp-Out Protection
For safety, the MAX8729 monitors the lamp-current feedback (IFB) to detect faulty or open CCFL lamps and shorted IFB sense resistor. As described in the Lamp-Current Regulation section, the voltage on IFB is internally full-wave rectified. If the rectified IFB voltage is below 790mV, the MAX8729 charges the TFLT capacitor with 1A. The MAX8729 latches off if the voltage on TFLT exceeds 4V. Unlike the normal shutdown mode, the linear regulator output (VCC) remains at 5.3V. Toggling SHDN or cycling the input power reactivates the device. During the delay period, the current-control loop tries to maintain the lamp-current regulation by increasing the high-side MOSFET on-time. Because the lamp impedance is very high when it is open, the transformer secondary rises as a result of the high-Q factor of the resonant tank. Once the secondary voltage exceeds the overvoltage threshold, the MAX8729 turns on a 1.2mA current source that discharges the COMP capacitor. The on-time of the high-side MOSFET is reduced, lowering the secondary voltage, as the COMP voltage decreases. Therefore, the peak voltage of the transformer secondary winding never exceeds the limit during the lamp-out delay period.
Primary Overcurrent Protection
VCC PS1 DIMMING ON/OFF CNTL SHDN MASTER HFCK LFCK PS2 HF LF PSCK DPWM
The MAX8729 provides cycle-by-cycle primary overcurrent protection. A current-sense amplifier monitors the drain-to-source voltages of both the high-side and low-side switches when the switches are conducting. If the voltage exceeds the internal current-limit threshold (400mV typ), the regulator turns off the high-side switch at the opposite side of the primary to prevent the transformer primary current from increasing further.
VCC PS1 VCC CNTL SHDN SLAVE 1 HFCK LFCK PSCK DPWM PS2 HF LF
Secondary Current Limit (ISEC)
The secondary current limit provides fail-safe protection in case of short-circuit or leakage from the transformer's high-voltage terminal to ground. ISEC monitors the voltage across a sense resistor placed between the transformer's low-voltage secondary terminal and ground. The ISEC voltage is internally half-wave rectified and continuously compared to the ISEC regulation threshold (1.25V, typ). Any time the ISEC voltage exceeds the threshold, a controlled current is drawn from COMP to reduce the on-time of the bridge's high-side switches. At the same time, the MAX8729 charges the TFLT capacitor with a 126A current. The MAX8729 latches off when the voltage on TFLT exceeds 4V. Unlike the normal shutdown mode, the linear regulator output (VCC) remains at 5.3V. Toggling SHDN or cycling the input power reactivates the device.
VCC PS1 CNTL SHDN SLAVE 2 HFCK LFCK PSCK DPWM PS2 HF LF
VCC PS1 CNTL SHDN SLAVE 4 HFCK LFCK PSCK DPWM PS2 HF LF
Synchronization in Daisy-Chain Operation (HFCK, LFCK, PSCK, DPWM)
The MAX8729 supports daisy-chain operation to allow synchronization and phase shift of multiple MAX8729s. Up to five MAX8729s can be connected in a daisychain configuration shown in Figure 6. Connecting CNTL to VCC enables the daisy-chain operation and puts the IC in slave mode. To synchronize the switching frequency, connect the HFCK pins of the slave IC and master IC together, and connect the PSCK pin of the master IC to the HF pin of
Figure 6. Daisy-Chain Operation of Five Controllers 18
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Constant-Frequency, Half-Bridge CCFL Inverter Controller
Table 1 Phase Shift Setting
PIN SETTING PS2 X GND GND VCC VCC PS1 X GND VCC GND VCC MASTER 0 0 0 0 0 N/A 180 120 90 72 PHASE SHIFT IN DEGREES SLAVE 1 SLAVE 2 N/A N/A 240 180 144 SLAVE 3 N/A N/A N/A 270 216 SLAVE 4 N/A NA N/A N/A 288 NO. OF PHASES 1 2 3 4 5
MAX8729
X = Don't care.
the slave IC. To synchronize the DPWM frequency, connect the LFCK pins of the slave IC and master IC together, and connect the DPWM pin of the master IC to the LF pin of the slave IC. The CNTL brightness control is disabled in the slave mode. The master directly controls the brightness setting of the slave by providing a dimming signal on its DPWM pin.
Linear Regulator Output (VCC)
The internal linear regulator steps down the DC input voltage to 5.35V (typ). The linear regulator supplies power to the internal control circuitry of the MAX8729. VCC can be used to power the MOSFET gate drivers by connecting it to VDD. VDD can also be driven from an external supply. The VCC voltage drops to 4.5V in shutdown.
Phase Shift in Daisy-Chain Operation (PS1, PS2)
The MAX8729 has the capability to adjust the phase of the gate drivers and the DPWM oscillator. The phaseshift function significantly reduces the input RMS ripple current and lowers the input capacitor requirement. The phase shift can be easily programmed using two logic input pins (PS1 and PS2). These two pins combined together give four choices of phase shift: 72, 90, 120, and 180. The selection of the phase shift is based on the number of MAX8729s used in the daisy-chain. Table 1 gives the suggested selection of phase shift for 1, 2, 3, 4, and 5 phases. For a given multiphase circuit, all master and slave ICs should use the same setting for PS1, PS2. Table 2 summarizes the MAX8729's operation in all modes.
UVLO
The MAX8729 includes an undervoltage lockout (UVLO) circuit. The UVLO circuit monitors the VCC voltage. When VCC is below 4.2V (typ), the MAX8729 disables both high-side and low-side gate drivers and resets the fault latch.
Low-Power Shutdown
When the MAX8729 is placed in shutdown, all functions of the IC are turned off except for the 5.3V linear regulator. In shutdown, the linear regulator output voltage drops to about 4.5V and the supply current is 6A (typ). While in shutdown, the fault latch is reset. The device can be placed into shutdown by pulling SHDN to its logic low level.
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Constant-Frequency, Half-Bridge CCFL Inverter Controller MAX8729
Table 2. Operation Summary
PIN NAME MASTER MODE USING INTERNAL OSCILLATORS MASTER MODE USING EXTERNAL SYNC SIGNAL (SYNC ONLY) MASTER MODE USING EXTERNAL SYNC SIGNAL (SYNC AND DIMMING) CNTL control is disabled. The external signal controls the brightness. Connect CNTL to an analog voltage in case the external sync signal is lost. Connect SEL to VCC. Switching frequency is controlled by the external sync signal. Connect a resistor to GND in case the external sync signal is lost. DPWM frequency is determined by the external sync signal. Connect a resistor to GND in case the external sync signal is lost. Connect to the HFCK pin of its slave controller. SLAVE MODE
CNTL
An analog voltage on CNTL sets the brightness.
An analog voltage on CNTL sets the brightness.
Connect CNTL to VCC. Brightness is controlled by the master.
SEL
Connect SEL to GND.
Connect SEL to GND. Switching frequency is controlled by the external sync signal. Connect a resistor to GND in case the external sync signal is lost. DPWM frequency is determined by the external sync signal. Connect a resistor to GND in case the external sync signal is lost. Connect to the HFCK pin of its slave controller.
Don't care. Connect to the PSCK pin of its master controller.
HF
Connect a resistor to GND to set the switching frequency.
LF
Connect a resistor to GND to set DPWM frequency.
Connect to the DPWM pin of its master controller. Connect to the HFCK pin of its master controller. Connect a 1M resistor to GND. Connect to the LFCK pin of its master controller. Connect a 1M resistor to GND. Not used. Connect to GND.
HFCK
Connect to the HFCK pin of its slave controller.
LFCK
Connect to the LFCK pin of its slave controller.
Connect to the LFCK pin of its slave controller.
Connect to the LFCK pin of its slave controller. Connect to a highfrequency external signal to sync the switching frequency. Connect a low-frequency external signal to sync the digital PWM frequency. The duty cycle of the external signal determines the brightness. Connect to the HF pin of its slave controller. Connect to the LF pin of its slave controller.
HSYNC
Not used. Connect to GND.
Connect to a high-frequency external signal to sync the switching frequency.
LSYNC
Not used. Connect to GND.
Connect a low-frequency external signal to sync the digital PWM frequency.
Not used. Connect to GND.
PSCK DPWM
Connect to the HF pin of its slave controller. Connect to the LF pin of its slave controller.
Connect to the HF pin of its slave controller. Connect to the LF pin of its slave controller.
Connect to the HF pin of its slave controller. Connect to the LF pin of its slave controller.
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Constant-Frequency, Half-Bridge CCFL Inverter Controller MAX8729
Applications Information
The MAX8729 requires two external n-channel power MOSFETs to form a half-bridge inverter circuit to drive the transformer primary. Since the positive half-cycle and negative half-cycle are symmetrical, the same type of MOSFET should be used for the high-side and lowside switches. When selecting the MOSFET, focus on the voltage rating, current rating, on-resistance (RDS(ON)), total gate charge, and power dissipation.
MOSFETs
Select a MOSFET with a voltage rating at least 25% higher than the maximum input voltage of the inverter. For example, if the maximum input voltage is 24V, the voltage rating of the MOSFET should be 30V or higher. The current rating of the MOSFET should be higher than the peak primary current at the minimum input voltage and full brightness. Use the following equation to estimate the primary peak current IPEAK_PRI: IPEAK _ PI = 2 xPOUT _ MAX VIN _ MIN x
tion losses plus the switching losses at both VIN_MIN and VIN_MAX. Calculate both terms. Ideally, the losses at VIN(MIN) should be roughly equal to the losses at VIN(MAX), with lower losses in between. If the losses at V IN(MIN) are significantly higher than the losses at VIN(MAX), consider increasing the size of the MOSFETs. Conversely, if the losses at VIN(MAX) are significantly higher than the losses at VIN(MIN), consider choosing MOSFETs with lower parasitic capacitance. If VIN does not vary over a wide range, the minimum power dissipation occurs where the conduction losses equal the switching losses. Calculate the total conduction power dissipation of the two MOSFETs using the following equation: PDCONDUCT = IPRI2 x RDS(ON) where IPRI is the primary current calculated using the following equation: IPRI = POUT _ MAX x VIN
where P OUT _ MAX is the maximum output power, VIN_MIN is the minimum input voltage, and is the estimated efficiency at the minimum input voltage. Assuming the half bridge drives four CCFLs and the maximum output power of each lamp is 4.5W, the total maximum output power is 18W. If the minimum input voltage is 8V and the estimated efficiency is 75% at that input, the peak primary current is approximately 4.3A. Therefore, power MOSFETs with a DC current rating of 5A or greater are sufficient. Since the regulator senses the on-state, drain-to-source voltage of both MOSFETs to detect the transformer primary current, the lower the MOSFET RDS(ON), the higher the current limit is. Therefore, the user should select n-channel MOSFETs with low RDS(ON) to minimize conduction loss, and keep the primary current limit at a reasonable level. Use the following equation to estimate the maximum and minimum values of the primary current limit: ILIM _ MIN = 320mV RDS(ON)_ MAX 480mV RDS(ON)_ MIN
Both MOSFETs turn on with ZVS condition, so there is no switching power dissipation associated with the MOSFET. However, the current is at peak when the MOSFET is turned off. Calculate the total turn-off switching power dissipation of the two MOSFETs using the following equation: PDSWITCH = 2 x CRSS x VIN2 x fSW x IPRI IGATE
where CRSS is the reverse transfer capacitance of the MOSFETs and IGATE is the peak gate-drive sink current when the MOSFET is being turned off.
ILIM _ MAX =
Both MOSFETs must be able to dissipate the conduc______________________________________________________________________________________ 21
Constant-Frequency, Half-Bridge CCFL Inverter Controller MAX8729
Setting the Lamp Current
The MAX8729 senses the lamp current flowing through resistor R1 (Figure 1) connected between the low-voltage terminal of the lamp and ground. The voltage across R1 is fed to IFB and is internally full-wave rectified. The MAX8729 controls the desired lamp current by regulating the average of the rectified IFB voltage. To set the RMS lamp current, determine R1 as follows: R1 = x 790mV 2 2 x ILAMP(RMS)
Setting the Secondary Current Limit
The MAX8729 limits the secondary current even if the IFB sense resistor is shorted or transformer secondary current finds its way to ground without passing through R1. ISEC monitors the voltage across the sense resistor R2 connected between the low-voltage terminal of the transformer secondary winding and ground. Determine the value of R2 using the following equation: R2 = 1.28V 2 x ISEC(RMS)_ MAX
where ILAMP(RMS) is the desired RMS lamp current and 790mV is the typical value of the IFB regulation point specified in the Electrical Characteristics table. To set the RMS lamp current to 6mA, the value of R1 should be 148. The closest standard 1% resistors are 147 and 150. The precise shape of the lamp-current waveform depends on lamp parasitics. The resulting waveform is an imperfect sinusoid waveform, which has an RMS value that is not easy to predict. A high-frequency true RMS current meter (such as Yokogawa 2016) should be used to measure the RMS current and make final adjustments to R1. Insert this meter between the sense resistor and the lamp's low-voltage terminal to measure the actual RMS current.
where I SEC(RMS)_MAX is the desired maximum RMS transformer secondary current during fault conditions, and 1.28V is the typical value of the ISEC peak voltage when the secondary is shorted. To set the maximum RMS secondary current in the circuit of Figure 1 to 22mA, set R3 = 40.2.
Transformer Design and ResonantComponent Selection
The transformer is the most important component of the resonant tank circuit. The first step in designing the transformer is to determine the transformer turns ratio. The ratio must be high enough to support the CCFL operating voltage at the minimum supply voltage. The transformer turns ratio N can be calculated as follows: N VLAMP(RMS) 0.45 x VIN(MIN)
Setting the Secondary Voltage Limit
The MAX8729 limits the transformer secondary voltage during startup and lamp-out faults. The secondary voltage is sensed through the capacitive voltage-divider formed by C3 and C4 (Figure 1). The voltage of VFB is proportional to the CCFL voltage. The selection of parallel resonant capacitor C3 is described in the Transformer Design and Resonant-Component Selection section. Smaller values for C3 result in higher efficiency due to lower circulating current. If C3 is too small, the resonant operation is affected by the panel parasitic capacitance. Therefore, C3 is usually chosen to be between 10pF and 18pF. After the value of C3 is set, select C4 based on the desired maximum RMS secondary voltage VLAMP(RMS)_MAX: C4 = 2 x VLAMP(RMS)_ MAX 2.34 V x C3
where VLAMP(RMS) is the maximum RMS lamp voltage in normal operation, and VIN(MIN) is the minimum DC input voltage. If the maximum RMS lamp voltage in normal operation is 800V and the minimum DC input voltage is 10V, the turns ratio should be greater than 178. The next step in the procedure is to design the resonant tank so the resonant frequency is close to the switching frequency set by the HF resistor. The lamp current is closer to sine wave when the switching frequency is close to the resonant frequency The resonant frequency is determined by: the primary capacitive voltage-divider CS1 and CS2, the secondary parallel capacitor CP, the transformer secondary leakage inductance L, and the CCFL lamp. The simplified CCFL inverter circuit is shown in Figure 7a. The half-bridge power stage is simplified and represented as a square-wave AC source. The resonant tank circuit can be further simplified to Figure 7b by removing the transformer. CS' is the capacitance of the primary capacitive divider reflected to the secondary and N is the transformer turns ratio.
where the 2.34V is the typical value of the VFB peakvoltage when the lamp is open. To set the maximum RMS secondary voltage to 1800V with C3 selected to be 12pF, C4 must be less than or equal to 13nF.
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Constant-Frequency, Half-Bridge CCFL Inverter Controller MAX8729
CS1 + CS2 1:N 4 L
3 CP
CCFL
AC SOURCE
VOLTAGE GAIN (V/V)
RL INCREASING 2
(a)
1
C'S = (CS1 + CS2) / N2
L
0
20
40
60
80
100
FREQUENCY (kHz) AC SOURCE
CP
RL
Figure 8. Frequency Response of the Resonant Tank
(b)
Figure 7. Simplified CCFL Inverter Circuit
Figure 8 shows the frequency response of the resonant tank's voltage gain under different load conditions. The primary series capacitor is 1F, the secondary parallel capacitor is 15pF, the transformer turns ratio is 1:78, and the secondary leakage inductance is 260mH. Notice that there are two peaks, fS and fP, in the frequency response. The first peak, fS, is the series resonant peak determined by the secondary leakage inductance (L) and the series capacitor reflected to the secondary (C'S): fS = 1 2 LC'S
nant peak due to the lamp's infinite impedance. The circuit displays the characteristics of a parallel-loaded resonant converter. While in parallel-loaded resonant operation, the inverter behaves like a voltage source to generate the necessary striking voltage. Theoretically, the output voltage of the resonant converter increases until the lamp is ionized or until it reaches the IC's secondary voltage limit. Once the lamp is ionized, the equivalent-load resistance decreases rapidly and the operating point moves toward the series-resonant peak. While in series-resonant operation, the inverter behaves like a current source. The leakage inductance of the CCFL transformer is an important parameter in the resonant tank design. The leakage inductance values can have large tolerance and significant variations among different batches. It is best to work directly with transformer vendors on leakage inductance requirements. The MAX8729 works best when the secondary leakage inductance is between 200mH and 350mH. The primary capacitive dividers C1 and C2 set the minimum operating frequency, which is approximately two times the seriesresonant peak frequency. Choose: C1 = C2 N2 8 2 x f 2 MIN x L
The second peak, fP , is the parallel resonant peak determined by the secondary leakage inductance (L), the parallel capacitor (CP), and the series capacitor reflected to the secondary (C'S): fP = 2 L 1 C'S CP C'S + CP
The actual resonant frequency is between these two resonant peaks. When the lamp is off, the operating point of the resonant tank is close to the parallel reso-
where fMIN is the minimum operating frequency range. In the circuit of Figure 1, the transformer's turns ratio is 178 and its secondary leakage inductance is about 300mH. To set the minimum resonant frequency to 40kHz, use a capacitor of 2.2F or less for C1 and C2.
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23
Constant-Frequency, Half-Bridge CCFL Inverter Controller MAX8729
Parallel capacitor C3 sets the maximum operating frequency, which is also the parallel-resonant peak frequency. Choose: C3 C1 + C2 4 2 x f 2 MAX x L x CS - N2 average charge current is around 30A, the rise time is about three times longer than the fall time.
Setting the Fault-Delay Time
The TFLT capacitor determines the delay time for both the open-lamp fault and secondary short-circuit fault. The MAX8729 charges the TFLT capacitor with a 1A current source during an open-lamp fault and charges the TFLT capacitor with a 126A current source during a secondary short-circuit fault. Therefore, the secondary short-circuit fault-delay time is approximately 100 times shorter than that of the pen-lamp fault. The MAX8729 sets the fault latch when the TFLT voltage reaches 4V. Use the following equations to calculate the open-lamp fault delay (T OPEN_LAMP ) and secondary short-circuit fault delay (TSEC_SHORT): TOPEN _ LAMP = C TFLT x 4 V 1A C x 4V TSEC _ SHORT = TFLT 126A
In the circuit of Figure 1, the maximum resonant frequency is 70kHz, C1 and C2 are 2.2F, and the secondary leakage inductance is 300mH. Therefore, use a capacitor of 12pF or greater for C3. The transformer core saturation should also be considered when selecting the operating frequency. The primary winding should have enough turns to prevent transformer saturation under all operating conditions. Use the following expression to calculate the minimum number of turns N1 of the primary winding: N1 > DMAX x VIN(MAX) BS x A x fMIN
where DMAX is the maximum duty cycle (approximately 0.8) of the high-side switch, VIN(MAX) is the maximum DC input voltage, BS is the saturation flux density of the core, and A is the minimal cross-section area of the core.
Bootstrap Capacitor
The high-side gate driver is powered using a bootstrap circuit. The MAX8729 integrates the bootstrap diode so only one 0.1F bootstrap capacitor is needed. Connect the capacitor between LX and BST to complete the bootstrap circuit.
COMP Capacitor Selection
The COMP capacitor sets the speed of the current-regulation loop that is used during startup, maintaining lamp-current regulation, and during transients caused by changing the input voltage. To maintain stable operation, the COMP capacitor (C COMP) needs to be at least 3.3nF. As discussed in the Digital PWM Dimming Control section, the COMP capacitor also limits the dynamics of the lamp-current envelope in digital PWM operation. At the end of the digital PWM ON cycle, the MAX8729 turns on a 100A internal current source to linearly discharge the COMP capacitor. Use the following equation to set the fall time: CCOMP = 100A x t FALL 1.5V
Layout Guidelines
Careful PC board layout is important to achieve stable operation. The high-voltage section and the switching section of the circuit require particular attention. The high-voltage sections of the layout need to be well separated from the control circuit. Follow these guidelines for good PC board layout: 1) Keep the high-current paths short and wide, especially at the ground terminals. This is essential for stable, jitter-free operation and high efficiency. 2) Use a star-ground configuration for power and analog grounds. The power and analog grounds should be completely isolated--meeting only at the center of the star. The center should be placed at the analog ground pin (GND). Using separate copper islands for these grounds can simplify this task. Quiet analog ground is used for VCC, COMP, HF, LF, and TFLT.
where tFALL is the fall time of the lamp-current envelope and 1.5V is the dynamic range of the COMP voltage. At the beginning of the digital PWM ON cycle, the COMP capacitor is charged by transconductance error amplifier, so the charge current is not constant. Because the
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Constant-Frequency, Half-Bridge CCFL Inverter Controller
3) Route high-speed switching nodes away from sensitive analog areas (V CC , COMP, HF, LF, and TFLT). Make all pin-strap control input connections to analog ground or VCC rather than power ground or VDD. 4) Mount the decoupling capacitor from VCC to GND as close as possible to the IC with dedicated traces that are not shared with other signal paths. 5) The current-sense paths for LX to GND and IN to LX must be made using Kelvin-sense connections to guarantee the current-limit accuracy. With 8-pin SO MOSFETs, this is best done by routing power to the MOSFETs from the outside using the top copper layer, while connecting GND and LX inside (underneath) the 8-pin SO package. 6) Ensure the feedback connections are short and direct. To the extent possible, IFB, VFB, and ISEC connections should be far away from the high-voltage traces and the transformer. 7) To the extent possible, high-voltage trace clearance on the transformer's secondary should be widely separated. The high-voltage traces should also be separated from adjacent ground planes to prevent lossy capacitive coupling. 8) The traces to the capacitive voltage-divider on the transformer's secondary need to be widely separated to prevent arcing. Moving these traces to opposite sides of the board can be beneficial in some cases.
Pin Configuration
TOP VIEW
PCOMP 1 SEL 2 IN 3 VCC 4 GND 5 TFLT 6 CNTL 7 SHDN 8 LF 9 LFCK 10 DPWM 11 PSCK 12 HFCK 13 HSYNC 14 28 VDD 27 GL 26 PGND 25 BST 24 GH
MAX8729
MAX8729
23 LX 22 PS1 21 LSYNC 20 ISEC 19 VFB 18 IFB 17 COMP 16 PS2 15 HF
QSOP
Chip Information
TRANSISTOR COUNT: 7531 PROCESS: BiCMOS
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25
Constant-Frequency, Half-Bridge CCFL Inverter Controller MAX8729
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE, QSOP .150", .025" LEAD PITCH
21-0055
E
1 1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
26 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.
QSOP.EPS

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